1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which can be cleared such that the data stored in all the memory cells are rewritten to the same values.
2. Description of the Related Art
Stated briefly, a semiconductor memory device is cleared by writing data "0" or "1" into each of its memory cells. The way in which a conventional SRAM is cleared will now be explained in detail, with reference to FIG. 1, which shows only a one-column section of a SRAM.
Assuming that data "1" is stored in a static memory cell MC, the potentials at nodes C and D of the flip-flop are then at a "1" level and a "0" level, respectively. How the data stored in memory cell MC is rewritten from "1" to "0" will now be described.
First, a row decoder (not shown) raises the potential on word line WL to the "1" level. As a result, N-type MOS FETs Q1 and Q2, whose gates are coupled to word line WL, are turned on. A column-selecting signal CD, which is an output of a column decoder (not shown) is raised to the "1" level. As a result, N-type MOS FETs Q3 and Q4, whose gates receive this signal CD, are also turned on. Inverters 1 and 2, which constitute a data-writing circuit, are driven by a write control circuit (not shown). Inverter 1 supplies a "1"-level signal to bit line te,ovs/BL/ , whereas inverter 2 supplies a "0"-level signal to bit line BL. As a result, current i3 flows to node D of the flip-flop, thus raising the potential at node D from the "0" level to the "1" level. This is because current i3 is the sum of current il flowing to node D from power-supply potential terminal V.sub.DD through bit line te,ovs/BL/ , and current i2 flowing to node D from terminal V.sub.DD through P-type MOS FET Q11 of inverter 1, N-type MOS FET Q4, and bit line te,ovs/BL/ .
On the other hand, the potential at node C of the flip-flop is lowered from the "1" level to the "0" level, since current i4 flows from node C to ground potential terminal V.sub.SS through N-type MOS FETs Q1 and Q3 and N-type MOS FET Q22 of inverter 2.
When the potential at node D rises from the "0" level to the "1" level, and the potential at node C falls from the "1" level to the "0" level, N-type MOS FETs Q7 and Q8 of the flip-flop are turned on and off, respectively. Hence, while the data stored in memory cell MC is being rewritten from "1" to "0", currents Il and, as is illustrated in FIG. 1, I2 continue flowing from power-supply potential terminal V.sub.DD to ground potential terminal V.sub.SS. Since neither current Il nor current I2 contributes to this data-writing process, it is obvious therefore, that a relatively large amount of power is wasted in the process of rewriting the data stored in memory cell MC.
To clear a semiconductor memory device, the data-writing operation described above must be performed in relation to all the memory cells incorporated in the memory device. Consequently, a very large amount of power is bound to be wasted every time the memory device is cleared.